Modern electronics, such as smart phones, personal digital assistants, location based services devices, enterprise class servers, or enterprise class storage arrays, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost. Contemporary electronics expose integrated circuits and packages to more demanding and sometimes new environmental conditions, such as cold, heat, and humidity requiring integrated circuit packages to provide robust structures.
Numerous technologies have been developed to meet these requirements. Some of the research and development strategies focus on new technologies while others focus on improving the existing and mature technologies. Research and development in the existing technologies may take a myriad of different directions.
Integrated circuit packages for complex electronic systems typically have a large number of interconnected integrated circuit chips. The integrated circuit chips are usually made from a semiconductor material such as silicon. After manufacture, the chips are typically incorporated into packages that are then mounted on printed circuit wiring boards.
Integrated circuit chip packages typically have numerous external pins that are mechanically attached by solder or a variety of other known techniques to conductor patterns on the printed circuit wiring boards.
Typically, the packages in which these integrated circuit semiconductor chips are mounted include a substrate or other chip mounting device. One example of such a substrate is a lead frame. More particularly, a lead frame is a metal frame that includes a centrally located die paddle or die pad and a plurality of peripherally-located leads that surround the die pad. The die pad mounts the semiconductor chip (or “die”). Power, ground, and/or signal leads of the lead frame are connected electrically by wire bonds to power, ground, and/or signal sites on the chip and serve as external connecting means for the chip.
After the chip is wire-bonded to the leads, the chip, the die pad, and portions of the leads are encapsulated in a plastic, an epoxy-molded compound, or a multi-part housing made of plastic, ceramic, or metal, to form the semiconductor package. The package protects the lead frame and the chip from physical, electrical, moisture, and/or chemical damage.
Some lead frame configurations, for example exposed die pad packages, include a separate ground ring structure that is supported around the periphery of the die pad and inside the inner ends of the leads. The ground ring facilitates the many bonding wire electrical connections that typically must be made to connect ground pads on the die to electrical ground connections on the lead frame.
Typically, the ground ring is coated with a metal, such as silver, to improve bonding adhesion between the wires and the ground ring. However, silver forms a weak adhesion with the encapsulation material. This may provide problems causing separation between the integrated circuit die from the die pad.
Integrated circuit packages, such as quad flat no-leaded (QFN) packages, surface mount for die attach paddle (DAP) are an option, which depend on application requirements. If DAP will be mounted, space beneath the DAP will not be available for routing, which in turn can result in increasing board size and/or reduced electrical performance. Conversely, some QFN package applications requiring thermal and electrical performance are being limited due to DAP not being mounted onto the printed circuit board.
Looking at other assembly aspects, wire bonding for QFN packages is becoming a challenge. I/O pitch continues to decrease in order to increase I/O density. The reduced I/O pitch also exacerbates flow of the molding compound at the I/O area leading to increased potential for molding compound delamination, especially with the silver on the ground ring. Down bonds are used for grounding application which in turn decreases the number of I/O available for signals. Higher moisture sensitivity level (MSL) requirements are also being sought for QFN packages due to its body size.
Thus, a need still remains for an integrated circuit package system providing low cost manufacturing, reduced form factor, and improved reliability for the integrated circuit package. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.